Co-authored-by: Andreas Kurth <akurth@iis.ee.ethz.ch>
Co-authored-by: Manuel Eggimann <meggimann@iis.ee.ethz.ch>

Rationale: The conversion from AXI-Lite to APB is fairly simple both for
requests and responses.  Thus, unless this needs to be clocked at very
high frequencies, it should be possible without a pipeline register.
This saves one cycle of latency for each request and one for each
response.  Since latency is presumably more critical for this conversion
that achieving maximum frequency, the default is changed to not insert
pipeline registers.

The registers cannot be completely omitted, however, because the
implementation relies on a default-ready behavior both for requests and
responses.  Fall-through registers, which are designed exactly for
adding the default-ready behavior, are thus instantiated when pipelining
is disabled.

We don't include testbench-internal changes in the Changelog, but
changes to dependencies need to be documented comprehensibly.

`common_verification` v0.2.0 has been released more than a year ago (but
is still the latest version), so it's about time to update.  This also
entails the following changes:

- Instances of modules from `common_verification` in our testbenches are
  updated.
- `common_cells` is updated to v1.21.0 to align on the same version of
  `common_verification`.

This patch makes it optional for a random slave to randomize the success
of any accesses. The default is off, so any existing code should be
still compatible.

Again, useful for achieving code coverage on error conditions of any
modules.

The upcoming release script will ensure there are two empty lines above
each release section.  Thus this change is done now to avoid noise in
subsequent release commits.

Combinatorial processes without explicit XXX can cause circular
dependencies which causes simulators to endlessly reschedule
a loop.  Different tools have different heuristics for detecting
this and breaking up loops.  This isn't an exact science, but the
following changes seems to avoid an endless loop under Vivado XSim.

Note: There is a small behavioural change in the code:

If `ax_valid` is asserted while `ax_select >= NoMstPorts` (where `x`
is `r` or `w`), the behaviour is undefined.  In the old code this would
just not assert the `ax_ready` flag.  This is only an issue if
`ax_select` for some reason gets out of bound, which probably causes
other issues.

On the upside, the new code likely uses slightly less logic.  If the
old behaviour is required, a check to see that the select signal is
in range could be added.  Alternatively, this could be added as an
assertion.
Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>

Just like Verilator, Vivado XSim does not handle the `iff` properties.
This patch wraps these properties into `ifndef XSIM` .. `endif`.
Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>

This is the second batch of fixes, which are not backwards-compatible.